Focus: deliver hardware-based cybersecurity for avionics buses — combining FPGA IP development with throughput- and latency-aware data-processing architecture for real-time applications.
Day-to-day responsibilities
FPGA IP Development
SystemVerilog IP for a data-bus processing device enforcing cybersecurity on legacy and emerging avionics buses.
Architecture Research
Researching and testing hardware-driven data-processing architectures to push throughput and shave latency for real-time avionics.
Host Interfaces
Implemented FPGA USB and SPI interfaces for configuration, control, and host data exchange.
RTL Verification
Designing, simulating, and verifying RTL with CocoTB and Vivado on AMD Xilinx FPGAs.
The work
The RCAT Lab focuses on cybersecurity for cyber-physical and embedded systems. My role sits squarely on the hardware side: a data-bus processing device targeting avionics environments where modern cybersecurity primitives must live alongside protocols originally designed for safety and determinism — not for adversarial threat models.
Day to day, that means writing SystemVerilog IP, validating it with CocoTB-based testbenches, and pushing designs through Vivado for AMD Xilinx FPGAs. Beyond the cybersecurity IP itself, I've also built the host-side plumbing — USB and SPI interfaces that let the device be configured, controlled, and fed data from a host system during development and integration.
Parallel to the implementation work, I've been researching hardware-driven data-processing architectures — evaluating trade-offs in throughput and latency that matter for real-time avionics applications, where the cost of a slow security check can be measured in microseconds.
What I'm taking away
Production-grade RTL workflow on commercial FPGA tooling (CocoTB + Vivado + AMD Xilinx hardware), hands-on experience with industrial avionics bus protocols, and a much sharper sense of how cybersecurity primitives translate from a software threat model into hardware design constraints.
Project specifics beyond what's described here are limited by the nature of the work.